UART0 output

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This page shows some debug output that comes from uart0

normal boot process

xosPe0 serial#x subid 0xc4
xenv cs2 ok
power supply: ok
dram0 ok (9)
dram1 ok (9)
zboot (0) ok
>
**********************************
* SMP863x zboot start ...
* Version: 2.0.0-2.7.112.1
* Started at 0x91000000.
* Configurations (chip revision: 4):
*    Use 8KB DRAM as stack.
*    Support XLoad format.
*    Enabled BIST mode.
*    Enabled memory test mode.
* PIRELLI-STB based on v.2.7.120.0 DDC-20060519).
**********************************
Boot from flash (0x48000000) mapped to 0xac000000.
Found XENV block at 0xac000000.
CPU clock frequency: 297.00MHz.
System clock frequency: 198.00MHz.
DRAM0 dunit_cfg/delay0_ctrl (0xf34111ba/0x000a9999).
DRAM1 dunit_cfg/delay0_ctrl (0xe34111ba/0x000a8898).
Using UART port 0 as console.
Board ID.: "Pirelli STB HY100"
Chip Revision: 0x8634:0x82 .. Mismatched.
Setting up H/W from XENV block at 0xac000000.
  Keeping <SYSCLK premux> to 0x00000203.
  Setting <SYSCLK avclk_mux> to 0x00000000.
  Setting <SYSCLK hostclk_mux> to 0x00000100.
  Setting <IRQ rise edge trigger lo> to 0xff28ca00.
  Setting <IRQ fall edge trigger lo> to 0x0000c000.
  Setting <IRQ rise edge trigger hi> to 0x0000009f.
  Setting <IRQ fall edge trigger hi> to 0x00000000.
  Setting <IRQ GPIO map> to 0x0d000a00.
  Setting <PB default timing> to 0x010e0008.
  Setting <PB timing0> to 0x010e0008.
  Setting <PB Use timing0> to 0x000003fc.
  Setting <PB timing1> to 0x00110101.
  Setting <PB Use timing1> to 0x000003f3.
  PB cs config: 0x000c10c0 (use 0x000c10c0)
  Enabled Devices: 0x00023efe
    BM/IDE PCIHost Ethernet IR FIP I2CM I2CS USB PCIDev1 PCIDev2 PCIDev3 PCIDev4 SCARD
  MAC: 00:17:c2:f0:36:04
  PCI IRQ routing:
    IDSEL 1: INTA(#14) INTB(#14) INTC(#14) INTD(#14) 
    IDSEL 2: INTA(#14) INTB(#14) INTC(#14) INTD(#14) 
    IDSEL 3: INTA(#14) INTB(#14) INTC(#14) INTD(#14) 
    IDSEL 4: INTA(#15) INTB(#15) INTC(#15) INTD(#15) 
  Smartcard pin assignments:
    OFF pin = 0
    5V pin = 1
    CMD pin = 2
  Setting up Clean Divider 2 to 96000000Hz.
  Setting up Clean Divider 4 to 33333333Hz.
  GPIO dir/data = 0x00000000/0x00000000
  UART0 GPIO mode/dir/data = 0x6e/0x00/0x00
  UART1 GPIO mode/dir/data = 0x6e/0x00/0x00
XENV block processing completed.
Found existing memcfg: DRAM0(0x08000000), DRAM1(0x04000000)
Default boot index: 0
Scanning ROMFS image at 0xac280000 (0x48280000) .. Found.
ROMFS found at 0xac280000, Volume name = YAMON_XRPC
Found 1 file(s) to be processed in ROMFS.
Processing xrpc_xload_yamon_ES4_prod.bin (start: 0xac280090, size: 0x00036d74)
  Checking zboot file signature .. Not found.
  Trying xrpc_xload format .. OK
  Checking zboot file signature at 0x13000000 .. OK
  Warning: header version mismatched.
  Decompressing to 0x91160000 .. OK (752304/0xb7ab0).
  Load time total 335 msec.
  Execute at 0x91160000 ..



selected scart OUT to display splash screen
File 31bitmap.zbf not found

inizio bitmap = 0x00000000


**********************************
* YAMON ROM Monitor - STANDARD -
* Revision 02.06-SIGMADESIGNS-01-2.7.112.1
**********************************
Memory:  code: 0x11000000-0x11040000, 0x11160000-0x11164000
reserved data: 0x111a0000-0x123a0000, PCI memory: 0x123a0000-0x127a0000
Environment variable 'start' exists. After 0 seconds
it will be interpreted as a YAMON command and executed.
Press Ctrl-C (or do BREAK) to bypass this.

Checking signature...

============================================
    FLASH IMAGE PARAMETERS:
--------------------------------------------
--> Image start address = 0xac4c0000
--> Signature start address = 0xac4c00c0
--> Signature length is = 16
--> OS start address = 0xac4c0100
--> OS size = 20659968 (0x13b3f00)
--> OS end address = 0xad874000
============================================


booting the 2nd image

xosPe0 serial#fx subid 0xc4
xenv cs2 ok
power supply: ok
dram0 ok (9)
dram1 ok (9)
zboot (0) ok
>

00000000ca90b222000000a4000000a404071f80
00000000ca90b222000000a4000000a404071f80
00000000ca90b222000000a4000000a404071f80
00000000ca90b222000000a4000000a404071f80
00000000ca90b222000000a4000000a404071f80
00000000ca90b222000000a4000000a404071f80
00000000ca90b222000000a4000000a404071f80
00000000ca90b222000000a4000000a404071f80
00000000ca90b222000000a4000000a404071f80
00000000ca90b222000000a4000000a404071f80
00000000ca90b222000000a4000000a404071f80
00000000ca90b222000000a4000000a404071f80
00000000ca90b222000000a4000000a404071f80
00000000ca90b222000000a4000000a404071f80
00000000ca90b222000000a4000000a404071f80
00000000ca90b222000000a4000000a404071f80

**********************************
* SMP863x zboot start ...
* Version: 2.0.0-2.7.112.1
* Started at 0x91000000.
* Configurations (chip revision: 4):
*    Use 8KB DRAM as stack.
*    Support XLoad format.
*    Enabled BIST mode.
*    Enabled memory test mode.
* PIRELLI-STB based on v.2.7.120.0 DDC-20060519).
**********************************
Boot from flash (0x48000000) mapped to 0xac000000.
Found XENV block at 0xac000000.
CPU clock frequency: 297.00MHz.
System clock frequency: 198.00MHz.
DRAM0 dunit_cfg/delay0_ctrl (0xf34111ba/0x000a9999).
DRAM1 dunit_cfg/delay0_ctrl (0xe34111ba/0x000a8898).
Using UART port 0 as console.
Board ID.: "Pirelli STB HY100"
Chip Revision: 0x8634:0x82 .. Mismatched.
Setting up H/W from XENV block at 0xac000000.
  Keeping <SYSCLK premux> to 0x00000203.
  Setting <SYSCLK avclk_mux> to 0x00000000.
  Setting <SYSCLK hostclk_mux> to 0x00000100.
  Setting <IRQ rise edge trigger lo> to 0xff28ca00.
  Setting <IRQ fall edge trigger lo> to 0x0000c000.
  Setting <IRQ rise edge trigger hi> to 0x0000009f.
  Setting <IRQ fall edge trigger hi> to 0x00000000.
  Setting <IRQ GPIO map> to 0x0d000a00.
  Setting <PB default timing> to 0x010e0008.
  Setting <PB timing0> to 0x010e0008.
  Setting <PB Use timing0> to 0x000003fc.
  Setting <PB timing1> to 0x00110101.
  Setting <PB Use timing1> to 0x000003f3.
  PB cs config: 0x000c10c0 (use 0x000c10c0)
  Enabled Devices: 0x00023efe
    BM/IDE PCIHost Ethernet IR FIP I2CM I2CS USB PCIDev1 PCIDev2 PCIDev3 PCIDev4 SCARD
  MAC: 00:17:c2:f0:36:04
  PCI IRQ routing:
    IDSEL 1: INTA(#14) INTB(#14) INTC(#14) INTD(#14) 
    IDSEL 2: INTA(#14) INTB(#14) INTC(#14) INTD(#14) 
    IDSEL 3: INTA(#14) INTB(#14) INTC(#14) INTD(#14) 
    IDSEL 4: INTA(#15) INTB(#15) INTC(#15) INTD(#15) 
  Smartcard pin assignments:
    OFF pin = 0
    5V pin = 1
    CMD pin = 2
  Setting up Clean Divider 2 to 96000000Hz.
  Setting up Clean Divider 4 to 33333333Hz.
  GPIO dir/data = 0x00000000/0x00000000
  UART0 GPIO mode/dir/data = 0x6e/0x00/0x00
  UART1 GPIO mode/dir/data = 0x6e/0x00/0x00
XENV block processing completed.
Found existing memcfg: DRAM0(0x08000000), DRAM1(0x04000000)
Default boot index: 0
Boot Index (2)
Scanning ROMFS image at 0xaffa0000 (0x4bfa0000) .. Found.
ROMFS found at 0xaffa0000, Volume name = YAMON_XRPC
Found 1 file(s) to be processed in ROMFS.
Processing xrpc_xload_yamon_ES4_prod.bin (start: 0xaffa0090, size: 0x000326f4)
  Checking zboot file signature .. Not found.
  Trying xrpc_xload format .. OK
  Checking zboot file signature at 0x13000000 .. OK
  Decompressing to 0x91160000 .. OK (476512/0x74560).
  Load time total 300 msec.
  Execute at 0x91160000 ..



**********************************
* RAPPO_YAMON ROM Monitor (for MTC use only) version 1.0
* Revision 02.06-SIGMADESIGNS-01-2.7.120.1
**********************************
Memory:  code: 0x11000000-0x11040000, 0x11160000-0x11164000
reserved data: 0x111a0000-0x123a0000, PCI memory: 0x123a0000-0x127a0000
Found factory code. Autostart at 0xaf600000

Environment variable 'start' exists. After 2 seconds
it will be interpreted as a YAMON command and executed.
Press Ctrl-C (or do BREAK) to bypass this.
Found factory code. Autostart at 0xaf600000


  Checking zboot signature..  it's a zboot file, signature OK.
  Decompressing to 0x90020000 .. 
Output length: 0x0092b000(9613312)
load compressed zboot file from 0xaf600000 to 0x90020000 OK
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